Informatics Publishing Limited

Sushree Sila Panigrahy ¹, Neelam Rup Prakash ¹

Affiliations
1 Electronics and Electrical Engineering Department, PEC University of Technology, Chandigarh-160012, IN

Abstract

In this paper, techniques to build 1-bit full adders using less number of transistors are proposed. New design methodologies for the implementation of XOR and XNOR gates,which are the key components for full adder designs are presented here. This paper discusses two design methodologies for XOR and XNOR gates i.e. 3-T XOR and XNOR gates and Gate-Diffusion-Input (GDI) based XOR and XNOR gates. Two types of full adders are designed, 8-T full adders using 3-T XOR and XNOR gates and 10-T GDI based full adders. The adders are designed using low power technology. Almost all the new proposed adders consume less power as compared to the previously existing full adders due to lesser transistor count and their special structure. They also give improved performance in terms of delay and Power-Delay-Product (PDP), the deciding factors for efficiency measurement of the circuits.

Keywords

3-T XOR, 3-T XNOR, GDI, Full Adders, Delay, Low-Power, High-Speed.

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Sushree Sila Panigrahy ¹, Neelam Rup Prakash ¹

Affiliations
1 Electronics and Electrical Engineering Department, PEC University of Technology, Chandigarh-160012, IN

Abstract

In this paper a CMOS compatible novel Gate Diffusion input (GDI) logic structure is proposed. A novel GDI cell structure is quite similar to a CMOS inverter which has three input ports and one output port. The novel GDI logic is a low power design technique, which enables the implementation of a wide range of logic functions compared to the originally proposed basic GDI cell. This method allows reducing power consumption, delay and area for the design of basic logic gates and few logic functions by using lesser number of transistors than static CMOS logic, while maintaining low complexity of logic design. Logic gates are the basic building blocks for any type of circuit design. So, it is necessary to implement logic gates with minimum power consumption by reducing the transistor count for which novel GDI is a suitable technique to use. A variety of logic gates and functions have been implemented in 1.25 μm CMOS technology. A comparison between static CMOS logic and the proposed novel GDI cell designs has been analyzed. In comparison with conventional static CMOS logic, the novel GDI logic cells achieve reduction in power consumption as well as reduction in power delay product.

Keywords

Gate Diffusion Input (GDI), Logic Functions, Low Power, Static CMOS.

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Sukhwinder Singh ¹, Neelam Rup Prakash ²

Affiliations
1 PEC University of Technology, Chandigarh, IN
2 E & EC Department, PEC University of Technology, Chandigarh, IN

Abstract

Recent research in image processing has been strongly influenced by new developments in de noising techniques. Salt-and-pepper impulse noise is one commonly encountered noise type during image and video communication. Various methods have been implemented for the removal of this type of noise. This paper presents a new approach which first detects the noisy pixels using the binary flag image and then replaces only those pixels which are corrupted and the good pixels kept untouched. It is indicated that this method outperformed several existing methods in both visual image quality and restored signal quantity and gives high PSNR & IEF.

Keywords

Salt & Pepper Noise, Switching Median Filter, Decision Based Median Filter.

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Anshu Vishnoi ¹, Neelam Rup Prakash ²

Affiliations
1 H.B.T.I., Kanpur, IN
2 PEC, Chandigarh, IN

Abstract

Identification of gene locations in a DNA sequence is one of the important problems in the area of genomics. Nucleotides in exons of a DNA sequence show f=1/3 periodicity. The period-3 property in exons of eukaryotic gene sequences enables signal processing based time-domain and frequency domain methods to predict these regions. Identification of the period-3 regions helps in predicting the gene locations within the billions long DNA sequence of eukaryotic cells. In this paper the DNA symbolic-to-numeric representations are presented and the existing methods of gene prediction are also discussed. Finally, an enhancement over the existing methods has been proposed that combines the features of two best existing computationally efficient methods namely, AMDF (Average Magnitude difference function) and the optimized method. The proposed method improves upon the existing methods in terms of gene prediction accuracy.

Keywords

AMDF, Binary Indicator Sequence, Complex Indicator Sequence, DFT, DNA, EIIP Indicator Sequence, Gene Prediction, Paired Numeric, Period-3, Protein Coding, Roc.

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